When designing digital logic circuits with any sort of programmability there is often a tradeoff that must be made between speed and flexibility. Ideally, a circuit would have both high speed and functional flexibility, but, in practice, functional flexibility is generally achieved only at the expense of speed, and vice versa.
In FIG. 1, a programmable logic device having a programmable AND plane 11 followed by an OR plane with macrocells 13 is shown. The device has k inputs received by the AND plane 11 and m outputs provided by the OR plane and macrocells 13. The OR plane 13 itself receives l product term lines from the AND plane 11, and if sequential logic is provided, the device will also have n feedback lines from the macrocells back into the AND plane.
Macrocells for such programmable logic devices provide a number of options related to the device outputs, such as output enable and disable control, inverted or noninverted output signal polarity, stored or nonstored output signals, and selectable output pin utilization by multiple logic array blocks. Further, most macrocells also provide the capability of feeding one or more logic signals back into the programmable AND plane. Examples of typical macrocells are described in U.S. Pat. Nos. 4,124,899; 4,609,986; 4,684,830; 4,717,912; 4,758,746; 4,771,285; 4,789,951; 4,879,481; 4,894,563; and 4,912,345.
By way of illustration, one such macrocell is shown in FIG. 2. A logic signal representing the result of carrying out a specified function by programmable logic is received on a macrocell input line 12 connected, for example, to an output of an OR gate of the programmable logic. The macrocell input 12 is connected to a conductive line 14, which in turn has an inverter 15 connected to a side branch of the conductive line 14. Macrocell input 12 is also connected to an input D of a storage register or flip-flop 16 with complementary outputs Q and Q connected to lines 17 and 18. Four versions of the received logic signal are thus derived and presented on inputs 14, 15, 17 and 18 to a multiplexer 19, i.e. a noninverted nonstored signal, an inverted nonstored signal, a noninverted stored signal, and an inverted stored signal. The multiplexer 19 responsive to control signals provided by programmable switches, such as EPROMs, selects one of the four signal variants and transmits that selected signal to its output 20. A tristatable driver 22 responsive to an output enable signal EN transmits the signal to an input/output pin 24. Conductive lines 26, 28 and 30 from the macrocell input 12, register output Q and an input/output pin, respectively, connect to a feedback multiplexer 36. Thus, three signals, a nonstored logic signal, a stored logic signal and an input or output signal, are presented to the multiplexer 36, which selects one of them for feedback along conductive line 42 to the programmable logic, for example, to an input of a programmable AND array. Conductive lines 43 and programmable switches 45a, 45b, etc., can connect pins to an adjacent macrocell for efficient use of pin resources.
Such programmable logic devices are highly flexible and capable of being programmed to carry out a large number of possible logic functions, but are normally slow, because the capacitance on the various signal lines and the large number of programmable switches cause delays when signal levels are changed. A typical throughput for a programmable logic device made using a 1 .mu.m CMOS process is about 5.5 ns.
In contrast, an example of a conventional hardwired CMOS combinatorial logic circuit, shown in FIG. 3, is significantly faster, with a typical throughput of only 0.75 ns. Such a circuit is fast because it has only a few stages of conventional CMOS logic gates, but it lacks functional flexibility. Similar circuits with logic gates can be given a limited amount of flexibility with nearly the same speed as the fixed function circuit of FIG. 3, by including, for example, one or more multiplexers or by providing logic gates with a programmable number of inputs.
In some applications, one or more signals need to be operated upon quickly with combinatorial logic that varies too much according to a particular situation or set of conditions or that is too complex for simple hardwired logic gates to handle. Generally, programmable logic devices are used for such applications because they are capable of being programmed to carry out any one of a large number of possible logic functions and because they are able to carry out very complex logic. However, such devices are not especially fast, as already noted, and are generally not able to operate quickly on any signal. Even the macrocells, which could be constructed to receive some inputs directly from external pins for output enable or clocking, and which generally are relatively fast, are not expected to perform any combinatorial logic on signals they receive. Any additional logic needed by such signals are provided by feeding back these signals to the programmable logic via feedback lines in the macrocells.
An object of the present invention is to provide digital logic circuit combining the functional flexibility of programmable logic devices and the fast operation of fixed CMOS combinatorial logic to perform flexible logic on a fast input.